Main dipoles of the CNAO accelerator: some general features and systematic effects associated with fluxmeter-based magnetic measurements

LPSC-acc ;This report presents some general characteristics of the main synchrotron dipole magnets designed for the CNAO project. It gives some estimates of field integrals and magnetic field flux using the TOSCA field maps. Then it aims to evaluate some systematic effects associated to the magnetic measurements planned with the fluxmeter, especially designed to characterize the CNAO dipoles. All of what follows was performed at maximum magnetic field without magnet shimming

Contaminants Reduction in ECR Charge Breeders by LNL LPSC GANIL Collaboration

Contaminants reduction in Electron Cyclotron Resonance Charge Breeders (ECRCB) is a key point for the future experiments foreseen at LNL and GANIL Isotope Separation On Line (ISOL) facilities. According to the mass separator resolution set downstream the ECRCB, the radioactive ion beam study can be challenged in case of low production rate. An ongoing collaboration between LNL, LPSC and GANIL laboratories aims to improve the beam purity, acting on all the pollutant causes. Comparative experiments will be done at LPSC using different techniques, like covering the plasma chamber wall with liners of different materials. Different configurations of the ECRCB will also be tested, with the enhancement of the efficiency and charge breeding time parameters as additional objectives. A presentation of this program is proposed together with the recent upgrade of the LPSC 1+N+ test bench, with the aim to improve the vacuum quality

Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used

Measurement of fast and thermal neutron flux from the d + D reaction using the activation method

LPSC-acc ;

SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2 MeV Neutrons

This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP3). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed

Statistical Deviations from the Theoretical only-SBU Model to Estimate MCU rates in SRAMs

This paper addresses a well-known problem that occurs when memories are exposed to radiation: the determination if a bitflip is isolated or if it belongs to a multiple event. As it is unusual to know the physical layout of the memory, this paper proposes to evaluate the statistical properties of the sets of corrupted addresses and to compare the results with a mathematical prediction model where all of the events are SBUs. A set of rules easy to implement in common programming languages can be iteratively applied if anomalies are observed, thus yielding a classification of errors quite closer to reality (more than 80% accuracy in our experiments)

Single Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode

A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported